1. Field of Invention
Embodiments of the invention relate in general to Integrated Circuits (ICs). More specifically, the embodiments of the invention relate to methods and systems for physical placement of an integrated circuit based on the timing constraints of the integrated circuit.
2. Description of the Background Art
Designing an integrated circuit with millions of logic gates is a complex operation. While performing physical placement of an IC, timing closure is performed iteratively to obtain optimal timing performance. Timing closure can be defined as a process by which timing results on all paths in the IC are met according to standards as defined by the IC technology used and the product specifications. Timing closure becomes a challenging task for an IC with millions of logic gates. A part of the timing closure task involves timing budget allocation on various paths in the IC and further satisfying these timing budgets. A timing budget is a distribution of the available time for a signal to reach from a first node in a path to a second node in the path. Timing budget allocation includes development of timing constraints for the paths in the IC. Various techniques are available for facilitating timing budget allocation.
Conventional techniques may involve methods that assign every Input/Output (I/O) port a fixed delay or a fixed percentage of the clock period while writing block level timing constraints for the IC. When these conventional techniques are applied globally in the IC design, the timing budget allocation may not be precise and result in non-optimal timing results. Therefore, the conventional techniques may not predict the timing performance of the individual paths precisely. As a result, the individual paths may be over-constrained or under-constrained. An over-constrained path can be a path for which timing constraints are tighter than what can be fulfilled by a placement/synthesis tool. In the process of placing over-constrained paths, the placement/synthesis tool will waste time trying to meet unachievable timing constraints. Further, the placement/synthesis tool will also work harder than necessary on a path that could negatively affect other paths. Therefore, the task of fulfilling the timing constraints for an over-constrained path by the synthesis tool can be unnecessarily time consuming. Furthermore, an under-constrained path can be a path for which timing constraints are more lenient than what can be fulfilled by the placement/synthesis tool. Therefore, if a large number of paths are under-constrained, then the synthesis tool might quit the task of creating optimal timing results pre-maturely, considering the improvements made by this task to be insignificant in the overall timing performance. Further, while timing an inter-block path that has under-constrained block level timing constraints, the timing constraints for the block level may be satisfied but the timing constraints for the top level may not be satisfied, resulting in failing timing results for the top level. Therefore, the timing performance of a path in the IC is not optimized due to over-constrained and under-constrained paths.
Other conventional techniques may involve manual writing of timing constraints for the IC. But writing the timing constraints and analyzing the timing performance manually for tens or hundreds of thousands of paths in the IC is a cumbersome task. Conventional techniques try to reduce the number of required constraints by treating each bit of a data bus in the same way, i.e., the entire data bus is treated as a single timing problem. However, equal treatment of all bits may not result in an optimal solution since each bit may have a different level of combinational logic processing, depending on the design of the IC.
Various Electronic Design Automation (EDA) tools are used to perform top-level timing closure. The problem with such EDA tools is that they may provide top-level timing correction only for an inter-block path, which is failing to operate according to timing constraints. Moreover, this timing correction may only be a best-effort timing correction as it may not be able to modify the placement of certain elements in a path of the IC. Further, these tools may not consider the slack available anywhere else in the design for timing budget allocation. Therefore, using only existing EDA tools alone may result in non-optimal timing budget allocation and therefore non-optimal timing results.